The present disclosure is related to lithography, and more particularly to methods for using a charged particle beam writer to manufacture a surface which may be a reticle, a wafer, or any other surface.
In the production or manufacturing of semiconductor devices, such as integrated circuits, optical lithography may be used to fabricate the semiconductor devices. Optical lithography is a printing process in which a lithographic mask or photomask manufactured from a reticle is used to transfer patterns to a substrate such as a semiconductor or silicon wafer to create the integrated circuit. Other substrates could include flat panel displays or even other reticles. Also, extreme ultraviolet (EUV) or X-ray lithography are considered types of optical lithography. The reticle or multiple reticles may contain a circuit pattern corresponding to an individual layer of the integrated circuit, and this pattern can be imaged onto a certain area on the substrate that has been coated with a layer of radiation-sensitive material known as photoresist or resist. Once the patterned layer is transferred the layer may undergo various other processes such as etching, ion-implantation (doping), metallization, oxidation, and polishing. These processes are employed to finish an individual layer in the substrate. If several layers are required, then the whole process or variations thereof will be repeated for each new layer. Eventually, a combination of multiples of devices or integrated circuits will be present on the substrate. These integrated circuits may then be separated from one another by dicing or sawing and then may be mounted into individual packages. In the more general case, the patterns on the substrate may be used to define artifacts such as display pixels, holograms, or magnetic recording heads.
In the production or manufacturing of semiconductor devices, such as integrated circuits, maskless direct write may also be used to fabricate the semiconductor devices. Maskless direct write is a printing process in which charged particle beam lithography is used to transfer patterns to a substrate such as a semiconductor or silicon wafer to create the integrated circuit. Other substrates could include flat panel displays, imprint masks for nano-imprinting, or even reticles. Desired patterns of a layer are written directly on the surface, which in this case is also the substrate. Once the patterned layer is transferred the layer may undergo various other processes such as etching, ion-implantation (doping), metallization, oxidation, and polishing. These processes are employed to finish an individual layer in the substrate. If several layers are required, then the whole process or variations thereof will be repeated for each new layer. Some of the layers may be written using optical lithography while others may be written using maskless direct write to fabricate the same substrate. Eventually, a combination of multiples of devices or integrated circuits will be present on the substrate. These integrated circuits are then separated from one another by dicing or sawing and then mounted into individual packages. In the more general case, the patterns on the surface may be used to define artifacts such as display pixels, holograms, or magnetic recording heads.
Two common types of charged particle beam lithography are variable shaped beam (VSB) and character projection (CP). These are both sub-categories of shaped beam charged particle beam lithography, in which a precise electron beam is shaped and steered so as to expose a resist-coated surface, such as the surface of a wafer or the surface of a reticle. In VSB, these shapes are simple shapes, usually limited to rectangles of certain minimum and maximum sizes and with sides which are parallel to the axes of a Cartesian coordinate plane, and triangles with their three internal angles being 45 degrees, 45 degrees, and 90 degrees of certain minimum and maximum sizes. At pre-determined locations, doses of electrons are shot into the resist with these simple shapes. The total writing time for this type of system increases with the number of shots. In character projection (CP), there is a stencil in the system that has in it a variety of apertures or characters which may be rectilinear, arbitrary-angled linear, circular, nearly circular, annular, nearly annular, oval, nearly oval, partially circular, partially nearly circular, partially annular, partially nearly annular, partially nearly oval, or arbitrary curvilinear shapes, and which may be a connected set of complex shapes or a group of disjointed sets of a connected set of complex shapes. An electron beam can be shot through a character on the stencil to efficiently produce more complex patterns on the reticle. In theory, such a system can be faster than a VSB system because it can shoot more complex shapes with each time-consuming shot. Thus, an E-shaped pattern shot with a VSB system takes four shots, but the same E-shaped pattern can be shot with one shot with a character projection system. Note that VSB systems can be thought of as a special (simple) case of character projection, where the characters are just simple characters, usually rectangles or 45-45-90 degree triangles. It is also possible to partially expose a character. This can be done by, for instance, blocking part of the particle beam. For example, the E-shaped pattern described above can be partially exposed as an F-shaped pattern or an I-shaped pattern, where different parts of the beam are cut off by an aperture. This is the same mechanism as how various sized rectangles can be shot using VSB. In this disclosure, partial projection is used to mean both character projection and VSB projection.
As indicated, in optical lithography the lithographic mask or reticle comprises geometric patterns corresponding to the circuit components to be integrated onto a substrate. The patterns used to manufacture the reticle may be generated utilizing computer-aided design (CAD) software or programs. In designing the patterns the CAD program may follow a set of pre-determined design rules in order to create the reticle. These rules are set by processing, design, and end-use limitations. An example of an end-use limitation is defining the geometry of a transistor in a way in which it cannot sufficiently operate at the required supply voltage. In particular, design rules can define the space tolerance between circuit devices or interconnect lines. The design rules are, for example, used to ensure that the circuit devices or lines do not interact with one another in an undesirable manner. For example, the design rules are used so that lines do not get too close to each other in a way that may cause a short circuit. The design rule limitations reflect, among other things, the smallest dimensions that can be reliably fabricated. When referring to these small dimensions, one usually introduces the concept of a critical dimension. These are, for instance, defined as the smallest width of a line or the smallest space between two lines, those dimensions requiring exquisite control.
One goal in integrated circuit fabrication by optical lithography is to reproduce on the substrate the original circuit design by use of the reticle. Integrated circuit fabricators are always attempting to use the semiconductor wafer real estate as efficiently as possible. Engineers keep shrinking the size of the circuits to allow the integrated circuits to contain more circuit elements and to use less power. As the size of an integrated circuit critical dimension is reduced and its circuit density increases, the critical dimension of the circuit pattern or physical design approaches the resolution limit of the optical exposure tool used in optical lithography. As the critical dimensions of the circuit pattern become smaller and approach the resolution value of the exposure tool, the accurate transcription of the physical design to the actual circuit pattern developed on the resist layer becomes difficult. To further the use of optical lithography to transfer patterns having features that are smaller than the light wavelength used in the optical lithography process, a process known as optical proximity correction (OPC) has been developed. OPC alters the physical design to compensate for distortions caused by effects such as optical diffraction and the optical interaction of features with proximate features. OPC includes all resolution enhancement technologies performed with a reticle.
OPC may add sub-resolution lithographic features to mask patterns to reduce differences between the original physical design pattern, that is, the design, and the final transferred circuit pattern on the substrate. The sub-resolution lithographic features interact with the original patterns in the physical design and with each other and compensate for proximity effects to improve the final transferred circuit pattern. One feature that is used to improve the transfer of the pattern is a sub-resolution assist feature (SRAF). Another feature that is added to improve pattern transference is referred to as “serifs”. Serifs are small features that can be positioned on a corner of a pattern to sharpen the corner in the final transferred image. It is often the case that the precision demanded of the surface manufacturing process for SRAFs is less than that for patterns that are intended to print on the substrate, often referred to as main features. Serifs are a part of a main feature. As the limits of optical lithography are being extended far into the sub-wavelength regime, the OPC features must be made more and more complex in order to compensate for even more subtle interactions and effects. As imaging systems are pushed closer to their limits, the ability to produce reticles with sufficiently fine OPC features becomes critical. Although adding serifs or other OPC features to a mask pattern is advantageous, it also substantially increases the total feature count in the mask pattern. For example, adding a serif to each of the corners of a square using conventional techniques adds eight more rectangles to a mask or reticle pattern. Adding OPC features is a very laborious task, requires costly computation time, and results in more expensive reticles. Not only are OPC patterns complex, but since optical proximity effects are long range compared to minimum line and space dimensions, the correct OPC patterns in a given location depend significantly on what other geometry is in the neighborhood. Thus, for instance, a line end will have different size serifs depending on what is near it on the reticle. This is even though the objective might be to produce exactly the same shape on the wafer. It is conventional to discuss the OPC-decorated patterns to be written on a reticle in terms of main features, that is features that reflect the design before OPC decoration, and OPC features, where OPC features might include serifs, jogs, and SRAF. To quantify what is meant by slight variations, a typical slight variation in OPC decoration from neighborhood to neighborhood might be 5% to 80% of a main feature size. Note that for clarity, variations in the design of the OPC are what is being referenced. Manufacturing variations, such as line-edge roughness and corner rounding, will also be present in the actual surface patterns. When these OPC variations produce substantially the same patterns on the wafer, what is meant is that the geometry on the wafer is targeted to be the same within a specified error, which depends on the details of the function that that geometry is designed to perform, e.g., a transistor or a wire. Nevertheless, typical specifications are in the 2%-50% of a main feature range. There are numerous manufacturing factors that also cause variations, but the OPC component of that overall error is often in the range listed. OPC shapes such as sub-resolution assist features are subject to various design rules, such as a rule based on the size of the smallest feature that can be transferred to the wafer using optical lithography. Other design rules may come from the mask manufacturing process or, if a character projection charged particle beam writer is used to form the pattern on a reticle, from the stencil manufacturing process. It should also be noted that the accuracy requirement of the SRAF features on the mask may be lower than the accuracy requirements for the main features on the mask.
Inverse lithography technology (ILT) is one type of OPC technique. ILT is a process in which a pattern to be formed on a reticle is directly computed from a pattern which is desired to be formed on a substrate such as a silicon wafer. This may include simulating the optical lithography process in the reverse direction, using the desired pattern on the surface as input. ILT-computed reticle patterns may be purely curvilinear—i.e. completely non-rectilinear —and may include circular, nearly circular, annular, nearly annular, oval and/or nearly oval patterns. Since curvilinear patterns are difficult and expensive to form on a reticle using conventional techniques, rectilinear approximations of the curvilinear patterns may be used. In this disclosure ILT, OPC, source mask optimization (SMO), and computational lithography are terms that are used interchangeably.
There are a number of technologies used for forming patterns on a reticle, including using optical lithography or charged particle beam lithography. If charged particle beam lithography is used, the total writing time increases with the number of shots. Reticle writing for the most advanced technology nodes typically involves multiple passes of charged particle beam writing, a process called multi-pass exposure, whereby the given shape on the reticle is written and overwritten. Typically, two to four passes are used to write a reticle to average out precision errors in the charged particle beam writer, allowing the creation of more accurate photomasks. Also typically, the list of shots, including the dosages, is the same for every pass. In one variation of multi-pass exposure, the lists of shots may vary among exposure passes, but the union of the shots in any exposure pass covers the same area. Multi-pass writing can reduce over-heating of the resist coating the surface. Multi-pass writing also averages out random errors of the charged particle beam writer. Multi-pass writing using different shot lists for different exposure passes can also reduce the effects of certain systemic errors in the writing process.
A layout pattern, such as a post-OPC pattern, must be decomposed or fractured into a set of VSB and/or CP shots so that a charged particle beam writer can expose the pattern onto a surface using the set or list of shots. Conventional fracturing tools generate a set of non-overlapping or disjoint shots of constant dosage, the dosage subject to later adjustment by proximity effect correction (PEC). Some charged particle beam writers require that the pre-PEC shot dosage be constant, since they do not allow dosage assignment on a shot-by-shot basis. Such charged particle beam writers perform PEC correction internally after reading the input shot list. More recently, U.S. patent application Ser. No. 12/202,366, filed Sep. 1, 2008 and entitled “Method and System For Design Of A Reticle To Be Manufactured Using Character Projection Lithography”, and U.S. patent application Ser. No. 12/473,265, filed May 27, 2009 and entitled “Method And System For Design Of A Reticle To Be Manufactured Using Variable Shaped Beam Lithography” disclose fracturing methods using overlapping shots.
The cost of charged particle beam lithography is directly related to the time required to expose a pattern on a surface, such as a reticle or wafer. Conventionally, the exposure time is related to the number of shots required to produce the pattern. For the most complex integrated circuit designs, forming the set of layer patterns, either on a set of reticles or on a substrate, is a costly and time-consuming process. Therefore, there exists a need to reduce the time required to form complex patterns, such as curvilinear patterns, on a reticle and other surfaces, such as by reducing the number of shots required to form these complex patterns and by overcoming shot overlap and shot dosage limitations of charged particle beam writer systems.